Hardware description languages are text based methods of describing digital hardware. A computer can then synthesize that into something that can be physically implemented.
VHDL -> Very-high-speed integrated circuit Hardware Description Language
The standard logic package also defines the basic logic operations (AND, OR, etc.), and there are other packages in the IEEE library that define numeric operations like addition and subtraction. You specify which packages to use with a "USE" statement. So the top of a VHDL file will often look something like this:
LIBRARY IEEE; -- Include the IEEE library
USE IEEE.STD_LOGIC_1164.ALL; -- Enable standard logic 1164
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- Enable unsigned interpretation for numbers
USE IEEE.STD_LOGIC_ARITH.ALL; -- Enable arithmetic operations on numbers
A VHDL file defines two aspects of a device:
What the device looks like from the outside, as an ENTITY. Most importantly, this describes the PORTs of the device — its input and output signals.
ENTITY statement is important for hierarchical design, because once your device is finished, if it is then used within another device, the only thing that matters is what signals go into it and what signals come out of it. Those can then be wired up within the larger device without needing to worry about the details of what's inside your device
Signals in the PORT statement can be input, output, or inout. If a port signal is an input, that signal can drive logic within the device (because something outside is going to be driving it), and the device itself cannot drive it. Outputs are the opposite: the device must assign a value (i.e. drive that signal), and the signal cannot drive any internal logic. Inout signals can work either way, but you need to be careful that only one device (be it your device or an external device) drives the signal at any given time. And remember, these are signals, not anything like a "variable" in a programming language. Think of them as wires with voltage on them (because that's what they end up being in the synthesized hardware).
How the device behaves. This is the ARCHITECTURE of the device — how it's built, namely what it does with the signals coming into it to produce the signals coming out of it.
This could be as simple as some combinational logic, or as complicated as an entire processor.
VHDL is case-insensitive, so "SignalA" is the same as "SiGNaLa". There isn't a widespread style convention for VHDL capitalization, so unless an employer provides one, you can use what looks best to you.
VHDL is whitespace agnostic. Spaces, tabs, and even newlines can be used as desired. You could put everything in the file on one line if desired.