D <= NOT A -> assigns d to not a
Y <= D AND C -> assigns y the inputs A and C
‘0’ : forcing logic 0,
‘1’ : forcing logic 1,
‘L’ : weak logic 0, such as a pull-down resistor,
‘H’ : weak logic 1, such as a pull-up resistor, and
‘W’ : weak unknown signal, as in what would occur if a node pulled up by a resistor were connected with one pulled down by a resistor,
‘Z’ : high impedance, not driven at all,
‘U’ : uninitialized, such as a signal that is the output of a flip-flop that has been turned on without a reset,
‘X’ : unknown, such as a signal that is being driven by multiple sources incorrectly,
‘-’ : "don’t care," used to indicate that the value can be chosen by the synthesizer.
-- Which libraries to include and which packages within them to use
library ieee;
use ieee.std_logic_1164.all;
entity MyDevice is -- Describes the device from the outside
port( -- Defines the signals coming into and out of the device
A : in std_logic; -- Items in the list separated by semicolons.
B : in std_logic;
C : in std_logic;
Y : out std_logic;
Z : out std_logic -- Note no semicolon because it's the last item of the list.
);
end MyDevice;
architecture MyInternals of MyDevice is -- Define the internal architecture of the device
-- Signals internal to the architecture can be declared here.
signal D : std_logic;
begin -- Begin the design of the architecture
-- This architecture just has simple combinational assignments.
Z <= D;
D <= A and B and C;
Y <= (not A and B) or (not B and C) or D;
end MyInternals;